This post was written in 2013, when I thought it was necessary to summarize infrastructure tools and flows needed in SoC design and verification, according to all my experience. Today when I checked on my old notes I found this one and would like to share it here. Later on I’ll update and expand this list according to my latest experience and knowledge in engineering tools and infrastructure for software and hardware development.
System-on-Chip design and verification process is a complicated one. Unlike the world of Web and Internet, the design and development of hardware products have higher risk and lower tolerance to any mistakes. SoC design and verification process requires collaborations from multiple teams and vendors. Lots of hard decisions to make. Lots of trade-offs to consider. Moreover, the nonrecurring-engineering (NRE) charge makes sufficient and solid verification a must with limited time and resource. Tools and automated flows are an essential part of any design house.
Here is a list of areas that need tools and flows for SoC software and hardware design and verification according to my experience.
| Usage Area of Tools/Flows | Software | Hardware | Design Usage | Verification Usage |
|---|---|---|---|---|
| Test Generation | x | x | x | |
| Regression System | x | x | x | |
| Coverage Reporting | x | x | x | |
| Coding Style Check | x | x | x | |
| Code Review System | x | x | x | |
| Code Quality Analysis | x | x | x | |
| Build System | x | x | x | x |
| Version Control | x | x | x | x |
| Integration System | x | x | x | |
| Spec System | x | x | ||
| RTL Generation | x | x | ||
| TestBench Generation | x | x | ||
| Synthesis | x | x | ||
| Netlist Quality Analysis | x | x | ||
| Power Analysis and Optimization | x | x | ||
| ECO Flow | x | x | ||
| Issue/Bug Tracking System | x | x | x | x |
| Infrastructure: Linux/Windows machines, LSF | x | x | x | x |